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GAO-QXPL-101-250×178
GAO-QXPL-101-250×178

GAOTek QSFP+ LR4 Transceiver with 40Gb/s (10Km)

ID: GAO-QXPL-101
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Overview

This 40Gbps, 1271/1331nm QSFP+ LR4 (Quad Small Form-factor Pluggable Plus) transceiver is used with a single-mode fiber to span upto 6.2 Miles (10km). They are compliant with the QSFP+ MSA and IEEE 802.3ba 40G QSFP+LR4.

Key Features

  • Compliant to IEEE 802.3ba and SFF 8436
  • Up to 6.2 Miles (10km) transmission on SMF
  • Up to 11.1Gbps Data rate per wavelength
  • 4 CWDM lanes Mux/Demux design
  • Electrically hot-pluggable
  • Digital Diagnostics Monitoring Interface
  • Compliant with QSFP+ MSA with LC connector
  • Power dissipation < 3.5 W
  • ROHS Compliant
  • Case operating temperature range from 32°F to 158°F (0°C to 70°C)

Technical Specifications

Protocol 2-wire serial communication
Working Range Up to 6.2 Miles (10km)
Standards IEEE 802.3ba

SFF-8436

Data rate 40 Gb/s
Wavelength 1271/1331nm
Transmitter Extinction Ratio 3.5 dB
Receiver Sensitivity -11.5 dBm
Receiver Input Saturation Power 2.3 dBm
Dimensions 2.83 in x 0.72in x0.33in( 72×18.35×8.5 mm)
Supply Voltage -0.3 to 4V
Storage Temperature -40 °F to 185 °F (-40°C to 85°C)
Storage Ambient Humidity 5% to 95%
Case Operating Temperature 32°F to 158°F (0°C to 70°C)

Standards

  • Compliant to IEEE 802.3ba
  • Compliant to SFF-8436
  • RoHS Compliant

Notes:

  1. GND is the symbol for signal and supply (power) common for QSFP+ modules. All are common within the QSFP+ module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
  2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP+ transceiver module in any combination. The connector pins are each rated for a maximum current of 500mA.

Optical Characteristics

Notes:

  1. Measured with a PRBS 2 31 -1 test pattern, @10.325Gb/s, BER

Electrical Characteristics

Notes:

  1. Connected directly to TX data input pins. AC coupled thereafter.
  2. Or open circuit.
  3. Into 100 ohms differential termination.
  4. 20 – 80 %.
  5. Loss Of Signal is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.
  6. Receiver sensitivity is compliant with power supply sinusoidal modulation of 20 Hz to 1.5 MHz up to specified value applied through the recommended power supply filtering network.

Digital Diagnostic Functions

GAOTek GAO-QXPL-101 support the 2-wire serial communication protocol as defined in the QSFP+ MSA which allows real-time access to the following operating parameters:

  • Transceiver temperature
  • Laser bias current
  • Transmitted optical power
  • Received optical power
  • Transceiver supply voltage

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP+ transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP+ transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP+ transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP+ devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 -QSFP+ Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.

For more detailed information including memory map definitions, please see the QSFP+ MSA Specification.

Lower Memory Map

The lower 128 bytes of the 2-wire serial bus address space, see below Table, is used to access a variety of measurements and diagnostic functions, a set of control functions, and a means to select which of the various upper memory map pages are accessed on subsequent reads. This portion of the address space is always directly addressable and thus is chosen for monitoring and control functions that may need to be repeatedly accessed. The definition of identifier field is the same as page 00h Byte 128.

Table 1: Lower Memory Map

Status Indicator Bits

The Status Indicators are defined in the below table.

Interrupt Flags

A portion of the memory map (Bytes 3 through 21), form a flag field. Within this field, the status of LOS and Tx Fault as well as alarms and warnings for the various monitored items is reported. For normal operation and default state, the bits in this field have the value of 0b. For the defined conditions of LOS, Tx Fault, module and channel alarms and warnings, the appropriate bit or bits are set, value = 1b. Once asserted, the bits remained set (latched) until cleared by a read operation that includes the affected bit or reset by the ResetL pin. The Channel Status Interrupt Flags are defined in below Table.

Table: Channel Status Interrupt Flags

The Module Monitor Interrupt Flags are defined in the below table.

The Channel Monitor Interrupt Flags are defined in the below Table.

Module Monitors

Real time monitoring for the QSFP+ module include transceiver temperature, transceiver supply voltage, and monitoring for each transmit and receive channel. Measured parameters are reported in 16-bit data fields, i.e., two concatenated bytes. These are shown in the below Table.

Table: Module Monitoring Values

Channel Monitoring

Real time channel monitoring is for each transmit and receive channel and includes optical input power , Tx bias current and Tx output Power. Measurements are calibrated over vendor specified operating temperature and voltage and should be interpreted as defined below. Alarm and warning threshold values should be interpreted in the same manner as real time 16-bit data. Table below defines the Channel Monitoring.

Table: Channel Monitoring Values

Control Bytes

Control Bytes are defined in below Table.

LPMode

The LPMode pin shall be pulled up to Vcc in the QSFP+ module. This function is affected by the LPMode pin and the combination of the Power_over-ride and Power_set software control bits (Address A0h, byte 93 bits 0,1).

The module has two modes a low power mode and a high power mode. When the module is in a low power mode it has a maximum power consumption of 1.5W. This protects hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted. A truth table for the relevant configurations of the LPMode and the Power_over-ride and Power_set are shown in Table 9. At Power up, the Power_over-ride and Power_set bits shall be set to 0.

Table: Power Mode Truth Table

Host-Transceiver Interface Block Diagram

Outline Dimensions

Applications

  • 40G Ethernet
  • Data Center and LAN

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