- Up to 25.78Gbps Data rate per wavelength
- Up to 1.2 Miles (2 Km) transmission on SMF
- 4 CWDM lanes Mux/De-mux design
- CWDM TOSA integrated Driver
- Build in CDR on both TX and RX
- Electrically hot-pluggable
- Digital Diagnostics Monitoring Interface
- Compliant with QSFP28 MSA with LC connector
- Power dissipation < 3.5 W
- SFF 8436 and ROHS Compliant
- Case operating temperature range from 32°F to 158°F (0°C to 70°C)
|Protocol||2 Wire Serial Communication|
|Working Range||Up to 1.2 Miles (2km)|
|Data rate||100 Gb/s|
|Transmitter Extinction Ratio||3.5 dB|
|Receiver Sensitivity||-10 dBm|
|Dimensions||4.8 in x 0.72 in x0.33in(122×18.35×8.5 mm)|
|Supply Voltage||-0.3 to 4V|
|Storage Temperature||-40 °F to 185 °F (-40°C to 85°C)|
|Storage Ambient Humidity||5% to 95%|
|Case Operating Temperature||32°F to 158°F (0°C to 70°C)|
- Compliant to IEEE 802.3ba and 100G CLR4/CWDM4
- Compliant to SFF-8436
- RoHS Compliant.
- GND is the symbol for signal and supply (power) common for QSFP28 modules. All are common within the QSFP28 module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
- VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP28 transceiver module in any combination. The connector pins are each rated for a maximum current of 500mA.
- Connected directly to TX data input pins. AC coupled thereafter.
- Or open circuit.
- Into 100 ohms differential termination.
- 20 – 80 %.
- Loss Of Signal is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.
- Receiver sensitivity is compliant with power supply sinusoidal modulation of 20 Hz to 1.5 MHz up to specified value applied through the recommended power supply filtering network.
Digital Diagnostic Functions
GAOTek GAO-QXP28L-102 support the 2-wire serial communication protocol as defined in the QSFP28 MSA which allows real-time access to the following operating parameters:
- Transceiver temperature
- Laser bias current
- Transmitted optical power
- Received optical power
- Transceiver supply voltage
The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.
This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed for more detailed information including memory map definitions; please see the QSFP28 MSA Specification.
Host-Transceiver Interface Block Diagram
- 100G Ethernet &100GBASE-LR4
- ITU OTU4