GAOTek QSFP28 LR4 Transceiver QXP28L-102, 100Gb/s and up to 2km

Standards

• Compliant to IEEE 802.3ba, IEEE 802.3bm and 100G LR4
• Compliant to SFF-8436
• RoHS Compliant.

PIN Assignment:

Notes:

1. GND is the symbol for signal and supply (power) common for QSFP28 modules. All are common within the QSFP28 module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP28 transceiver module in any combination. The connector pins are each rated for a maximum current of 500mA.

Optical Characteristics

Notes:

 1.

Electrical Characteristics

Notes:

1. Connected directly to TX data input pins. AC coupled thereafter.
2. Or open circuit.
3. Into 100 ohms differential termination.
4. Loss Of Signal is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.

Digital Diagnostic Functions

GAOTek GAO-QXP28L-101 support the 2-wire serial communication protocol as defined in the QSFP28 MSA which allows real-time access to the following operating parameters:

• Transceiver temperature
• Laser bias current
• Transmitted optical power
• Received optical power
• Transceiver supply voltage

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed.

For more detailed information including memory map definitions; please see the QSFP28 MSA Specification.

Host-Transceiver Interface Block Diagram

Outline Dimensions

Applications

• 100G Ethernet &100GBASE-LR4